Dear Job Seekers
Please find below the JD for one of our MNC located @ Hyderabad. Kindly go through the same and send me your CV to abhay@connectprosearch.com
You can also refer some of your friends if they are interested.
Level:
Senior Engineer or MTS ( lead)- HYDERABAD
Posting : Hyderabad
Urgency: Immediate
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Experience of 6+ years in functional verification of
complex ASIC/Microprocessor designs.
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Should have thorough hands-on experience in development of
chip level and/or block level test-bench env using
SystemVerilog/Verilog/C/C++/’e’/ASM and verification execution experience all
the way from specification through chip tape-out. This should encompass
functional coverage, DFT verification and gatesims verification. SoC
Architecture experience involving x86 architecture, DDR, PCI-e, PLLs and DFT
features is desired.
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Expertise in SoC design/testbench debug.
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Desired exposure to state-of-art methodologies/tools like
VMM/OVM/Specman/Vera
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Should be independent in planning and execution, self
motivated, key team player and excellent communication skills to interface in a
multi-site working environment.
·
Should be enthusiastic to learn new functional domains and
methodologies.
ü
Verification
–COE- HYDEREABAD
Internal Job
Description : Member of the
Verification COE’s global verification infrastructure group. Provide support to
India verification teams in the local time zone. Maintain and develop new
features for configuration management, job submission and regression failure
analysis tools. Develop regression framework and tests for VCOE tools. Provide
feedback from India teams to the VCOE tool and methodology planning process.
Work closely with VCOE teams in Boston and Austin. Requires skill with Unix
system programming, Perl, Ruby, C++, mysql databases, Verilog, System Verilog,
and/or LSF job distribution facilities.
External Job
Description : Verification
infrastructure maintenance and development engineering position. This employee
will support local hardware verification engineers with use of global, AMD-wide
tools, maintain those tools via bug fixes and test generation, and develop new
features. Tools include but are not limited to configuration management, job
distribution to multiple simulation farms, regression signature failure
analysis, functional coverage analysis and verification bus functional models.
Candidate must have experience in many or all of Unix system programming, Perl,
Ruby, C++, mysql databases, Verilog, System Verilog, LSF job distribution
facilities.
Thanks,
Sudhakar
ü
DFT
–GPG- HYDERABAD
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Job Description
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The candidate will be responsible for participating in the
pre-silicon block and system level design for Integrated Graphics chipsets. The
candidate will also be responsible for Front-End chip implementation including
design, synthesis and execution flows that starts with RTL coding and ends with
the delivery of a netlist package ready for physical design. Responsible for
synthesis, netlist generation, timing and logical equivalency checks,
floorplanning, budgeting, clock methodology and timing constraint management.
Candidate will work in collaboration with Physical Design Engineers in chip
level planning and integrations.
REQUIREMENTS
- At least 7-10 years
experience in complex ASIC Design. Direct experience in SOC or Graphics/Video is
plus.
- Have in depth
knowledge of entire design process from Design specification, defining
architecture, micro-architecture, RTL design and functional verification,
synthesis, Physical Design, Timing closure, Tape-out, and post-Si
debug.
- Have hands-on
experience in Chiplevel Design/Integration activities.
- Some Physical Design
exposure required.
- Should be able to
Lead a team, and provide Technical mentoring and guidance to junior
engineers.
- Perform Synthesis
and netlisting tasks such as SDC Development, Scan Insertion, ECO
implementation, Formal Verification, etc.
- Some exposure to
DFT is a strong plus.
- Work with Physical
Design team on Floor Plan, budgeting, timing closure, Signal Integrity, ECO
flows, Power analysis, IO PAD placement, etc.
- Should have
expertise in: Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC.
Good knowledge of datapath compilers is required.
- Should have
proficiency in flow development and scripting.
- Expertise in Perl
and Tcl is a must.
- Should be able to
work closely with RTL Designers and Backend Physical Design teams across
multiple sites.
- Must have good
communication & Analytical thinking skills.
- Knowledge of chip
bus interfaces such as AHB and various standard peripherals & interfaces is
a plus.
- Bachelor/Master/
Degree in Electrical or Computer Engineering
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ü
RTL-
Verificaiton –GPG- HYDERABAD
KEY RESPONSIBILITIES
The candidate will be
responsible for participating in the pre-silicon blocks and system level design
for the Integrated Graphics chipsets. The candidate will also be responsible for
Front-End chip implementation including design, implementation and execution of
the flow that starts with Micro-arch, RTL code and ends with the delivery of a
netlist package ready for physical design. The candidate will also be
responsible for synthesis, netlist generation, timing and logical equivalency
checks, floorplanning, budgeting, clock methodology and timing constraint
management. Work in collaboration with Physical Design Engineers in chip level
planning and integrations.
REQUIREMENTS
- At least 7-10 years
experience in complex ASIC Design and Verification, direct experience in SOC or
Graphics/Video is plus.
- Hands on knowledge
on chip bus interfaces such as AHB and various standard peripherals &
interfaces.
- Lead design team to
successfully complete block level/full chip design
- Work through entire
design process from producing Design specification, defining architecture,
micro-architecture, implementing reasonably complicated designs in Verilog and
functional verification.
- Knowledgeable in
Chiplevel Design/Integration activities
- Work closely with
Verification Team to develop testplans and testcases.
- Perform Synthesis
and netlisting tasks such as Constraint Development, LEC, STA, CDC. DFT is a
plus.
- Work with Physical
Design team on floor planning and Timing issues.
- Desired Tool
knowledge : Conformal LEC, Cadence RC, Perl, PrimeTime,
- Must have good
communication & Analytical thinking skills, ability and desire to work in
geographically diverse team environment
- Bachelor/Master/
Degree in Electrical or Computer Engineering
Responsibilities:
·
Responsible for
participating in the pre-silicon blocks, chip, multi-chip and system level
verification strategy for the Graphics chips
·
Specifying an
overall design verification plan for an full chip SoC
·
Specifying or
reviewing plans for complex blocks within the ASIC
·
Architecting new
verification methodologies and evaluating new tools.
·
Responsible for
developing complex verification environment using the latest coverage/assertions
based verification design methodology, which includes
:
o
self-checking,
reusable, automated verification environment : both at full-chip & block
level
o
Constrained random
generators and reference models
·
Being a mentor and
technical leader for more junior verification engineers.
·
Leading or
participating in the ASIC bring-up and debug
ü
DV-
GPG-
HYDERABAD
Job
Requirements and Skills:
·
B.E/B.Tech/M.E/M.Tech
in Electrical/Electronics Engineering
·
Minimum 7+ years
experience in ASIC Design Verification,
including 2 years as a verification lead
·
At least 2+ years
experience in complex ASIC Design Verification, direct experience in SOC or
Processor/Graphics/Video is preferred
·
Must
have excellent knowledge of ASIC Design Flow
·
Extensive
experience with C & C++ and SystemC
·
Experience
in developing complex testbench/model in verilog, PLI and/or System verilog
·
Excellent
debug skills in both functional and gate
level simulations are must.
·
Experience in random
test generation, coverage analysis, failure debug, formal equivalency checking,
and Assertions (PSL, SVA)
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Proficiency
in common UNIX scripting languages (perl, csh, sh.)
·
Knowledge
of I/O interfaces like USB2.0, SATA, SD and etc is desired
·
Knowledge
of 2D/3D Graphics, Video and Display standards is a plus
·
Must
have good communication skills and the ability and desire to foster a team
environment.
Thank
you
Abhay Kumar
9015212821
011-26186988
EMAIL- <a href=”mailto:abhay@connectprosearch.com” title=”blocked::mailto:abhay@connectprosearch.com
mailto:abhay@connectprosearch.com”>abhay@connectprosearch.com
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CONNECTPRO MANAGEMENT CONSULTANTS
116-B, Somdutt ChambersI, 5, Bhikaji Cama Place, New Delhi
- 110066
