Implementation -Job Description: MTS ( ASIC Design)

The candidate will be responsible for participating in the pre-silicon block and system level design for Integrated Graphics chipsets. The candidate will also be responsible for Front-End chip implementation including design, synthesis and execution flows that starts with RTL coding and ends with the delivery of a netlist package ready for physical design. Responsible for synthesis, netlist generation, timing and logical equivalency checks, floorplanning, budgeting, clock methodology and timing constraint management. Candidate will work in collaboration with Physical Design Engineers in chip level planning and integrations.

REQUIREMENTS

- At least 7-10 years experience in complex ASIC Design. Direct experience in SOC or Graphics/Video is plus.

- Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.

- Have hands-on experience in Chiplevel Design/Integration activities.

- Some Physical Design exposure required.

- Should be able to Lead a team, and provide Technical mentoring and guidance to junior engineers.

- Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification, etc.

-  Some exposure to DFT is a strong plus.

- Work with Physical Design team on Floor Plan, budgeting,  timing closure, Signal Integrity, ECO flows, Power analysis, IO PAD placement, etc.

- Should have expertise in: Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC. Good knowledge of datapath compilers is required.

- Should have proficiency in flow development and scripting.

- Expertise in Perl and Tcl is a must.

- Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.

- Must have good communication & Analytical thinking skills.

- Knowledge of chip bus interfaces such as AHB and various standard peripherals & interfaces is a plus.

- Bachelor/Master/ Degree in Electrical or Computer Engineering

Kindly send us your CV to abhay@connectprosearch.com for above mention position.
You can also refer some of your friends if they are interested. We’ll be really grateful to you.
Thanks
Rgds
Abhay Kumar
9015212821
011-26186988
EMAIL- abhay@connectprosearch.com
======================================================
Blog: http://connectpromanagementconsultants.wordpress.com
http://recruiterblogs.naukri.com/index.php?blog=1126&page=1&paged=1
URL: www.connectprosearch.com

MTS (Verification)

Key Responsibilities:

· Responsible for participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy for the Graphics chips

· Specifying an overall design verification plan for an full chip SoC

· Specifying or reviewing plans for complex blocks within the ASIC

· Architecting new verification methodologies and evaluating new tools.

· Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes :

o self-checking, reusable, automated verification environment : both at full-chip & block level

o Constrained random generators and reference models

· Being a mentor and technical leader for more junior verification engineers.

· Leading or participating in the ASIC bring-up and debug

Job Requirements and Skills:

· B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering

· Minimum 7+ years experience in ASIC Design Verification, including 2 years as a verification lead

· At least 2+ years experience in complex ASIC Design Verification, direct experience in SOC or Processor/Graphics/Video is preferred

· Must have excellent knowledge of ASIC Design Flow

· Extensive experience with C & C++ and SystemC

· Experience in developing complex testbench/model in verilog, PLI and/or System verilog

· Excellent debug skills in both functional and gate level simulations are must.

· Experience in random test generation, coverage analysis, failure debug, formal equivalency checking, and Assertions (PSL, SVA)

· Proficiency in common UNIX scripting languages (perl, csh, sh.)

· Knowledge of I/O interfaces like USB2.0, SATA, SD and etc is desired

· Knowledge of 2D/3D Graphics, Video and Display standards is a plus

Must have good communication skills and the ability and desire to foster a team environment

Kindly send us your CV to abhay@connectprosearch.com for above mention position.

You can also refer some of your friends if they are interested. We’ll be really grateful to you.

Thanks
Rgds
Abhay Kumar
9015212821
011-26186988
EMAIL- abhay@connectprosearch.com
======================================================
Blog: http://connectpromanagementconsultants.wordpress.com
http://recruiterblogs.naukri.com/index.php?blog=1126&page=1&paged=1
URL: www.connectprosearch.com

MTS ( ASIC Design)

KEY RESPONSIBILITIES

The candidate will be responsible for participating in the pre-silicon blocks and system level design for the Integrated Graphics chipsets. The candidate will also be responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with Micro-arch, RTL code and ends with the delivery of a netlist package ready for physical design. The candidate will also be responsible for synthesis, netlist generation, timing and logical equivalency checks, floorplanning, budgeting, clock methodology and timing constraint management. Work in collaboration with Physical Design Engineers in chip level planning and integrations.

REQUIREMENTS

- At least 7-10 years experience in complex ASIC Design and Verification, direct experience in SOC or Graphics/Video is plus.

- Hands on knowledge on chip bus interfaces such as AHB and various standard peripherals & interfaces.

- Lead design team to successfully complete block level/full chip design

- Work through entire design process from producing Design specification, defining architecture, micro-architecture, implementing reasonably complicated designs in Verilog and functional verification.

- Knowledgeable in Chiplevel Design/Integration activities

- Work closely with Verification Team to develop testplans and testcases.

- Perform Synthesis and netlisting tasks such as Constraint Development, LEC, STA, CDC. DFT is a plus.

- Work with Physical Design team on floor planning and Timing issues.

- Desired Tool knowledge : Conformal LEC, Cadence RC, Perl, PrimeTime,

- Must have good communication & Analytical thinking skills, ability and desire to work in geographically diverse team environment

- Bachelor/Master/ Degree in Electrical or Computer Engineering

 

Kindly send us your CV to abhay@connectprosearch.com for above mention position.
You can also refer some of your friends if they are interested. We’ll be really grateful to you.
Thanks
Rgds
Abhay Kumar
9015212821
011-26186988
EMAIL- abhay@connectprosearch.com
======================================================
Blog: http://connectpromanagementconsultants.wordpress.com
http://recruiterblogs.naukri.com/index.php?blog=1126&page=1&paged=1
URL: www.connectprosearch.com

CAD Flow Developers

From an EDA & ASIC company background

· Experience level: ~8 years

· Skills:

o Very strong in PERL, Shell scripting, developed flows and supported designs using Mentor, Synopsys, Cadence, Magma etc.

o Very good understanding of Design flow

o Show strong technical understanding of SoC design analysis (timing, noise/signal-integrity, EM, IR)

· Job description: Own and support CAD flows; develop methodology working closely with design projects. Individual contributor role with strong team player skills, should work with WW senior staffers

 

Kindly send us your CV to abhay@connectprosearch.com for above mention position.
You can also refer some of your friends if they are interested. We’ll be really grateful to you.
Thanks
Rgds
Abhay Kumar
9015212821
011-26186988
EMAIL- abhay@connectprosearch.com
======================================================
Blog: http://connectpromanagementconsultants.wordpress.com
http://recruiterblogs.naukri.com/index.php?blog=1126&page=1&paged=1
URL: www.connectprosearch.com

Install shield Developers

Position 1: Install – HYDERABAD

· 4+ years of experience in developing applications using C++, MFC, ATL, COM.

· 2+ years of experience in developing MSI packages (Install shield preferable).

· Experience in developing driver installations using DIFx Framework.

· Good understanding of Windows Installer and Windows Driver Model.

· Expert knowledge of Windows Operation systems (XP and Vista).

· Ability to learn new things and should be a team player

 

Kindly send us your CV to abhay@connectprosearch.com for above mention position.
You can also refer some of your friends if they are interested. We’ll be really grateful to you.
Thanks
Rgds
Abhay Kumar
9015212821
011-26186988
EMAIL- abhay@connectprosearch.com
======================================================
Blog: http://connectpromanagementconsultants.wordpress.com
http://recruiterblogs.naukri.com/index.php?blog=1126&page=1&paged=1
URL: www.connectprosearch.com

Core IO Library Lead

Location-Bangalore, India

Exp. Level: 1-3Years
Required Basic Qualifications: Good understanding of CMOS library core & IO circuits, and cell layouts. Familiar with device physics and fabrication process. Familiar with ESD and latch-up. Basic understanding of analog circuits simulation (hspice) and digital simulation (verilog). Familiar with functional and timing models of digital library cells. Good understanding of mixed-signal software tools like Cadence to do schematic capture, analog simulation, layout and physical verification. Basic knowledge of UNIX is required. Good expertise on PERL or C programming. Basic understanding of digital design flow.
Additional Preferred Qualifications: Hands on design of various types of core & IO library cells will be an advantage. Familiar with ESD & latch up checkers. Familiar with power management concepts and the design of library cells related to those. Familiar with place and route flow of digital design. Basic understanding of digital timing verification, reliability analysis of signal integrity, EMIR will be an advantage.
Familiar with database management like tools like Clearcase, DesignSync.
Primary and Secondary Responsibilities: Design, develop and support digital core cell or IO libraries. Design library cells, create a generic database of circuits to develop libraries. Review the complete library, run various checkers, fill QC forms and document minutes. Gather new requirements and design cells to meet those. Document the library requirements periodically and maintain database for the libraries and releases as required by library development procedures. Prepare change notes for new requirements and identify the various tasks to implement the changes. Identify methods and procedures to check and improve the quality of the cell libraries. Develop and maintain scripts that checks the quality of the libraries.
Work with project lead to schedule a library development and manage the development.
Complex Tasks:
Good at debug, with the little information provided by customers. Quick to response to changes in schedule, unplanned walk-ins. Good understanding of the cell libraries data and their impact on the digital flow of synthesis, place & route. Understand complex dependencies between various library deliverables and their impact on design flows.
Management/Organizational Skills: For the assigned library development, coordinate and interface within the team and with designers, platform manager and other PDK teams.
Team and People Skills: This position requires good communication skills (oral and written). Coordinate/lead the library development effort, interface with other development teams (Platform manager, CDK, Assura rules, SPICE Modeling Lab). Work closely with other team members, EDA flow team and designers in understanding the library requirements. Communicate the plans, progress and issues at appropriate level of detail to varied audiences.
Projects and Deliverables: Cadence cell library, place & route deliverables, timing and functional models, library flow documents.
Unique selling features of this position, team, or project: Cell libraries play a key role digital design flows. This position provides an opportunity to contribute to TI’s business by leading quality cell libraries for various business units at TI. Exposure to various mixed signal and digital design flows and state-of-art design tools. Opportunity to work on continuously improving the development and verification flows of cell libraries. This jobs also provides opportunity to grow as project lead handling multiple libraries and the design flows associated with those.

Kindly send us your CV to abhay@connectprosearch.com for above mention position.

You can also refer some of your friends if they are interested. We’ll be really grateful to you.
Thanks
Abhay
9015212821
URL: www.connectprosearch.com

IO library Lead

Location- Bangalore, India
Exp. Level: 1-3Years
Good understanding of CMOS library core & IO circuits, and cell layouts. Familiar with device physics and fabrication process. Familiar with ESD and latch-up. Basic understanding of analog circuits simulation (hspice) and digital simulation (verilog). Familiar with functional and timing models of digital library cells. Good understanding of mixed-signal software tools like Cadence to do schematic capture, analog simulation, layout and physical verification. Basic knowledge of UNIX is required. Good expertise on PERL or C programming. Basic understanding of digital design flow.
Preferred Qualifications: Hands on design of various types of core & IO library cells will be an advantage. Familiar with ESD & latch up checkers. Familiar with power management concepts and the design of library cells related to those. Familiar with place and route flow of digital design. Basic understanding of digital timing verification, reliability analysis of signal integrity, EMIR will be an advantage.
Familiar with database management like tools like Clearcase, DesignSync.
Primary and Secondary Responsibilities: Design, develop and support digital core cell or IO libraries. Design library cells, create a generic database of circuits to develop libraries. Review the complete library, run various checkers, fill QC forms and document minutes. Gather new requirements and design cells to meet those. Document the library requirements periodically and maintain database for the libraries and releases as required by library development procedures. Prepare change notes for new requirements and identify the various tasks to implement the changes. Identify methods and procedures to check and improve the quality of the cell libraries. Develop and maintain scripts that checks the quality of the libraries.
Work with project lead to schedule a library development and manage the development.
Complex Tasks:
Good at debug, with the little information provided by customers. Quick to response to changes in schedule, unplanned walk-ins. Good understanding of the cell libraries data and their impact on the digital flow of synthesis, place & route. Understand complex dependencies between various library deliverables and their impact on design flows.
Organizational Skills: For the assigned library development, coordinate and interface within the team and with designers, platform manager and other PDK teams.
Team and People Skills: This position requires good communication skills (oral and written). Coordinate/lead the library development effort, interface with other development teams (Platform manager, CDK, Assura rules, SPICE Modeling Lab). Work closely with other team members, EDA flow team and designers in understanding the library requirements. Communicate the plans, progress and issues at appropriate level of detail to varied audiences.
Projects and Deliverables: Cadence cell library, place & route deliverables, timing and functional models, library flow documents.
Unique selling features of this position, team, or project: Cell libraries play a key role digital design flows. This position provides an opportunity to contribute to TI’s business by leading quality cell libraries for various business units at TI. Exposure to various mixed signal and digital design flows and state-of-art design tools. Opportunity to work on continuously improving the development and verification flows of cell libraries. This jobs also provides opportunity to grow as project lead handling multiple libraries and the design flows associated with those.
To give a crisp note for the requirements, the following is how I see:
IO library Lead,Good expertise on CMOS IO library circuits,Flair for automation and good at scripting,Capable of leading a team of 3 people

Kindly apply: abhay@connectprosearch.com for above mention position.
Abhay Kumar
9015212821

http://connectprosearch.com

FPGA Verification Engineer

Job Location – Bangalore, India
Full-Time

FPGA Verification Engineer
The successful candidate will be responsible for developing verification environment, supplying and developing test cases for control path FPGAs that are begin developed in the HW organization.
Experience

• 8+ years DV experience in communication ASIC or FPGA
• Capable of developing testplans from architecture and micro-architecture spec
• Experience with building test benches for module level, chip level, and multi-chip level simulations
• Hands-on experience with lab debugging
• Familiar with Verilog and System Verilog
• Strong scripting skills in Perl and Tcl
• Excellent verbal and written communication skills and ability to work independently
• BSEE, MSE preferred

Kindly send us your CV to abhay@connectprosearch.com for above mention position.
You can also refer some of your friends if they are interested. We’ll be really grateful to you.
Thanks
Rgds
Abhay Kumar
9015212821
011-26186988
EMAIL- abhay@connectprosearch.com
======================================================
Blog: http://connectpromanagementconsultants.wordpress.com
http://recruiterblogs.naukri.com/index.php?blog=1126&page=1&paged=1
URL: www.connectprosearch.com

Symbian Driver developers

Job Location- Gr Noida Design Centre, India

Role:
To analyse the requirements, design, development & validation, mainly for the deveice drivers (like USB, SD/MMC, DMA, etc..) in the embedded environement
Educational Requirement: BE/B.Tech Computer Science
Exp: 1.5years-3years
Skills Required:
—————–
ARM experience desirable
ClearCase knowledge
Advantageous to have expertise on Symbian/S60 technologies Good understanding of hardware architecture
Experience in development/testing/integration/validation of Real-time embedded systems for handset/mobile phones, with good understanding of any operating systems, preferably on Symbian Hands on experience
Kindly send us your CV to abhay@connectprosearch.com for above mention position.
You can also refer some of your friends if they are interested. We’ll be really grateful to you.
Thanks
Rgds
Abhay Kumar
9015212821
011-26186988
EMAIL- abhay@connectprosearch.com
======================================================
Blog: http://connectpromanagementconsultants.wordpress.com
http://recruiterblogs.naukri.com/index.php?blog=1126&page=1&paged=1
URL: www.connectprosearch.com

DOCSIS Software developer

Job Location- Gr Noida Design Centre, India

Education Level Required – B.Tech(Computer Science), Years of Work Experience – 3 to 6, Desired Competencies:
C/C++, Risc Processor, Linux Programming, Networking protocols, QoS, Linux, Security, VoIP Embedded SW Domain Required acketCable, DOCSIS, Protocols knowledge : SIP/IMS,NCS/MGCP,RTP/RTCP,SNMP, Network Security Skills in Speech compression/DSP, telephony,Fax a plus.

Kindly send us your CV to abhay@connectprosearch.com for above mention position.
You can also refer some of your friends if they are interested. We’ll be really grateful to you.
Thanks
Rgds
Abhay Kumar
9015212821
011-26186988
EMAIL- abhay@connectprosearch.com
======================================================
Blog: http://connectpromanagementconsultants.wordpress.com
http://recruiterblogs.naukri.com/index.php?blog=1126&page=1&paged=1
URL: www.connectprosearch.com