Location-Bangalore, India
Exp. Level: 1-3Years
Required Basic Qualifications: Good understanding of CMOS library core & IO circuits, and cell layouts. Familiar with device physics and fabrication process. Familiar with ESD and latch-up. Basic understanding of analog circuits simulation (hspice) and digital simulation (verilog). Familiar with functional and timing models of digital library cells. Good understanding of mixed-signal software tools like Cadence to do schematic capture, analog simulation, layout and physical verification. Basic knowledge of UNIX is required. Good expertise on PERL or C programming. Basic understanding of digital design flow.
Additional Preferred Qualifications: Hands on design of various types of core & IO library cells will be an advantage. Familiar with ESD & latch up checkers. Familiar with power management concepts and the design of library cells related to those. Familiar with place and route flow of digital design. Basic understanding of digital timing verification, reliability analysis of signal integrity, EMIR will be an advantage.
Familiar with database management like tools like Clearcase, DesignSync.
Primary and Secondary Responsibilities: Design, develop and support digital core cell or IO libraries. Design library cells, create a generic database of circuits to develop libraries. Review the complete library, run various checkers, fill QC forms and document minutes. Gather new requirements and design cells to meet those. Document the library requirements periodically and maintain database for the libraries and releases as required by library development procedures. Prepare change notes for new requirements and identify the various tasks to implement the changes. Identify methods and procedures to check and improve the quality of the cell libraries. Develop and maintain scripts that checks the quality of the libraries.
Work with project lead to schedule a library development and manage the development.
Complex Tasks:
Good at debug, with the little information provided by customers. Quick to response to changes in schedule, unplanned walk-ins. Good understanding of the cell libraries data and their impact on the digital flow of synthesis, place & route. Understand complex dependencies between various library deliverables and their impact on design flows.
Management/Organizational Skills: For the assigned library development, coordinate and interface within the team and with designers, platform manager and other PDK teams.
Team and People Skills: This position requires good communication skills (oral and written). Coordinate/lead the library development effort, interface with other development teams (Platform manager, CDK, Assura rules, SPICE Modeling Lab). Work closely with other team members, EDA flow team and designers in understanding the library requirements. Communicate the plans, progress and issues at appropriate level of detail to varied audiences.
Projects and Deliverables: Cadence cell library, place & route deliverables, timing and functional models, library flow documents.
Unique selling features of this position, team, or project: Cell libraries play a key role digital design flows. This position provides an opportunity to contribute to TI’s business by leading quality cell libraries for various business units at TI. Exposure to various mixed signal and digital design flows and state-of-art design tools. Opportunity to work on continuously improving the development and verification flows of cell libraries. This jobs also provides opportunity to grow as project lead handling multiple libraries and the design flows associated with those.
Kindly send us your CV to abhay@connectprosearch.com for above mention position.
You can also refer some of your friends if they are interested. We’ll be really grateful to you.
Thanks
Abhay
9015212821
URL: www.connectprosearch.com
