Senior DFT Engineer

Job Posting Title	Senior DFT Engineer
Job Description	Senior DFT Engineer who will be responsible for all aspects of Design for Test for a complex SoC.
Div / Cost Center	04800061 – ARM MCU INDIA DESIGN
Job ID	2429BR
Basic Qualifications	* BE/ME in Electronics and Communication * 6+ years experience in SOC/IP level DFT planning/execution. * Thorough understanding of scan and ATPG concepts – Scan, ATPG, Pattern generation for Stuckat/Trans fault/IDDQ/Path delay, Compression * Silicon Bring up experience & ATE knowledge
Preferred Qualifications & Skills	* Should be able to define DFT architecture for MCU class devices – Digital/Analog/SRAM/ROM/Flash/IOs * Should be able to align with designers/PEs on implementing the right DFT strategies with optimal test cost/test time. * Should have good understanding of memory test strategies. * Should have understanding on timing/constraints and should be able to work with STA team in defining/debugging test mode constraints. * Should have good experience in setting up flows for RTL/Gate level simulations and debugging. * Should be able to define verification strategies for DFT logic – Testbenches/Assertions etc. * Good scripting skills(perl/awk/sed). * Experience with Synopsys or Mentor or Cadence DFT tools. * Should have Si Bring up experience and ATE knowledge
Unique Selling Features of the Job	* Work on DFT for complex SoCs in an advanced process node * Work on SoC with state of the art Flash and Analog components * High volume SoCs

 

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